Need help running the PCIe to DDR3 SDRAM reference design

In reply to STD_LOGIC ... see the attached screenshot to get a sense of the timing violations I saw.

Did you compile and build a SOF file for EP4SGX230KF40C2N (which is the specific non-engineering sample device I have)? Can you send me a copy so I can test it out?

Just for clarification, when you say, " most apps like these just generate incremental or pseudo random data." ... do you mean that the application generates data in my PC's random access memory (RAM) then moves it across the PCIe bus to the DDR3 memory on the board? How does the application access and generate the data in RAM (the reference document doesn't explain this).

Thanks,

Eric

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Electronics Engineer

Microwave and Communication Systems Branch

NASA Goddard Space Flight Center, Code 567

8800 Greenbelt Road, Greenbelt, Maryland 20771, USA

Building 25, Room S054, Mail Code 567.3

Phone: (301)-286-3439 Email: eric.j.harris@nasa.gov

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