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Altera_Forum
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16 years ago

Need help running the PCIe to DDR3 SDRAM reference design

I've purchased an Altera Stratix IV GX FPGA development kit. I am trying to run the PCIe to DDR3 SDRAM reference design which I downloaded from: https://www.altera.com/support/software/download...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I'll have to go back and copy/paste the errors/warning, but in general, they are related to timing violations as thepancake noticed.

A SOF file was built despite the timing violations but I wasn't able to get the application to work after programming the device.

Please also address the following ... as I understand it, this PCIe to DDR3 application is supposed to measure the throughput of data being transferred across the PCIe bus from a PC to the DDR3 memory on the FPGA card ... but where exactly does the data on the PC side come from ... is the data generated from the PC's RAM or does it come from the PC's harddrive?

Just a little more context here ... my eventual goal is measure the speed of transferring data from a set of raided solid state drives on my PC across a PCIe bus to the DDR3 memory on the Altera Stratix IV development board. I'm only using the aforementioned reference design to get a sense of how the PCI-Express-Mega-Core works and how fast data can be transferred.

Please give feedback on this.

Thanks,

Eric