Need help in developing logic!

Thanks for your suggestions. I am not asking anyone to write code for me. See my subject again and just signal detection can’t be someone’s entire project.

BTW, I had posted this same question on another forum and got a suggestion to ‘implement detector of the rising edge for the sync signal. You could implement counter (startingelectronics dot org/software/VHDL-CPLD-course/tut19-up-down-counter/ ) which would increment every rising edge of SYNC and on every time pulse (say 1ms using m clock), you would check if the counter changed.’

I have implement the logic, below is the code. But it is working only first time connection of sensor. When I disconnect the SYNC signal the output doesn’t goes to low. Please advice the changes, I am beginner in VHDL and not an expert.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity sync_detector is
    Port (  SYNC	: in  STD_LOGIC;		-- Input SYNC signal
	    PULSE	: in  STD_LOGIC;		-- Input 1.024ms pulse
	    OUTPUT      : out bit			-- tells SYNC status
				);
end sync_detector;
 
architecture Behavioral of sync_detector is
signal S0_s		: std_logic := '1';  
signal counter_running : std_logic := '0';
signal count   : STD_LOGIC_VECTOR (3 downto 0):= X"0";                   
 
begin
S0_s <= not(SYNC);
-- Process for 4-bit counter
	process(S0_s)
		begin
		if (S0_s'event and S0_s= '1') then
		  count <= count + '1';
		  counter_running <= '1';
		end if;
	end process;
	
-- Process to check counter running after each 1.024ms
	process(PULSE)
	begin
		if (PULSE'event and PULSE = '1') then
		 if counter_running = '1' then
		   OUTPUT <= '1';
		    else
		     OUTPUT <= '0';
		 end if;
		end if;
	end process;
	
end Behavioral;