Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- Your process that generates the clock is also triggered by the clock, which won't work. It's a bit like the chicken-and-egg problem ;) You should have two processes, one to generate the clock, and another one that triggers on it:
Clockgen: process
begin
clock <= not clock after 10 ns; --will give 50MHz clock
end process;
--- Quote End --- This does not have to be inside a process, as it is a simple 1 line statement. Also, remember do not put this kind of code in your synthesisable code. Keep them separate as a testbench and a counter. If you put this code in and tried to synthesise it you'll some odd things getting generated.