Open Side Menu
Skip to contentBrand Logo
Forums
BlogKnowledge BaseAltera.com
RegisterSign In
  1. Altera Community
  2. Forums
  3. Boards & Dev Kits

Forum Discussion

VANITH's avatar
VANITH
Icon for New Contributor rankNew Contributor
6 years ago

Need 5M240ZM100A5 CPLD SPI TIMING DETAILS

Need 5M240ZM100A5 CPLD SPI TIMING DETAILS

1 Reply

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    You may refer to ALTUFM SPI Timing Specification in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/max5_handbook.pdf

    Thanks.

    Best regards,

    KhaiY

Recent Discussions

  • ove's avatar
    Agilex5 Eagle ES, NIOS-V + TSE IP
    19 hours ago
    ove
  • dtheodor79's avatar
    CXL 2.0 support on the NEW Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile)
    1 day ago
    dtheodor79
  • madhan_m's avatar
    Device stopped receiving config data: Internal error (0x0000, 0x00000000, 0x1800).
    9 days ago
    madhan_m
  • Ahmed_Sayed's avatar
    Slow Runtime Performance in FIL Implementation on DE2-115 Using Ethernet
    9 days ago
    Ahmed_Sayed
  • aJan's avatar
    Agilex5 HPS2FPGA usage
    10 days ago
    aJan
Contact Us
Altera YoutubeAltera YoutubeAltera Twitter
  • Company Overview
  • Newsroom
  • Our Leaders
  • Careers
Subscribe to Altera Newsletter

© Altera Corporation | Terms of Use | Privacy Policy | Cookies | Trademarks | PSIRT

Altera Logo