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OlegT's avatar
OlegT
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Multiple MSI with Avalon-MM DMA example

Hello. I am working with C10GX eval kit. I use AN829 AlalonMM DMA design as a starting point. One MSI is working well. I want to use 4 ones. PCIe hip is confugured to use 4 MSI. In linux d...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Accordingly to PCIe user guide doc, you need to perform below 2 steps

  • Turn on "Export MSI/MSI-X conduit interfaces" setting in PCIe IP to enable internal MSI interface bus
  • Then create your own custom interrupt handler design to manage it


You can refer to page 99, chapter 8.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support of the user guide doc


Thanks.


Regards,

dlim


  • OlegT's avatar
    OlegT
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    This is true, if we are takng about FPGA side of the question.

    But I am asking about driver side. As I understand, the allocation of irq vector should not be dependant on whether custom interrupt handler is realized in FPGA or not.

    Isn't it?

    Who is ressponsible to set bits [6 : 4] (multiply message enable) of conrol register (0x50) ?

    Thank you.