MSI PCIE Interrupt set up using Avalon-MM PCIe Hard IP Core as a Qsys component...

Hi,

1. There is no timing requirement specified in the user guide. If rxm_irq is asserted on consecutive cycles without the deassertion
of all interrupt inputs, no MSI message is sent for subsequent interrupts. To avoid losing interrupts, software must ensure that all interrupt sources are cleared for each MSI message received.

2. You may refer to Figure 10-4 for the MSI Interrupt Signals Waveform. The minimum latency possible between app_msi_req and app_msi_ack
is one clock cycle.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf

3. Unfortunately, there is a limited number of example design available for older devices.

Thanks

Best regards,

KhaiY