Memory IP for PAC card

HI, Ok, I get what you are doing now. PAC card design flow is different from traditional Quartus design flow. You can't use Quartus flow to migrate your existing A10 evaluation board design to PAC card. PAC card design flow is developed based on the acceleration stack software where it will instantiate all the periphery IP (like PCIe, Ethernet and DDR4) nicely for user. User is expected to develop FPGA core logic AFU design only to interact with the FPGA periphery IP. You can check out AFU design development guideline in below link. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-afu-dev.pdf You can also find more doc guideline for A10 PAC card in below link https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/acceleration-card-arria-10-gx/documentation.html Thanks. Regards, dlim