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DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Memory IP for PAC card

When I use the Intel Arria10 development board, I can generate the memory example design and select the Arria10 development board, then copy the memory IP to my design and use it. However, I don’t see the PAC card option to generate the memory example design. Is there a quick and reliable way to generate memory example design and IP for PAC card? Or do I have a go into the menu and set all the parameters for the memory? The later one is very tedious and it is easy to make mistake.

Thanks

6 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    HI, Are you referring to the DDR4 memory on Intel A10 GX FPGA PAC card ? Intel PAC card comes with fixed DDR4 configuration on the board. PAC card is designed for usage model where user installed the acceleration stack software that will auto instantiate DDR4 memory + other transceiver channel as whole solution package nicely for user. There is no need and reason for user to manually configure DDR4 IP anymore. Therefore, there is no DDR4 IP example design like what Intel provided on other Arria 10 development kit board. Thanks. Regards, dlim
    • DNguy4's avatar
      DNguy4
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Dlim,

      Yes, I am referring to the DDR4 memory on Intel A10 FX FPGA PAC card. I installed the acceleration stack SW but i still cannot find the memory IP. I see some other IPs such as DDR4_mm_bridge IP, Altera 10G Ethernet MAC IP, PLL IP, CRC32 IP... but I cannot find the memory IP. Any idea?

      Thanks

      • DNguy4's avatar
        DNguy4
        Icon for Occasional Contributor rankOccasional Contributor
        6 years ago

        I mean Intel A10 GX FPGA PAC card.

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    HI, Sorry, I still didn't get your intention here. Can you clarify further ? As I mentioned earlier, for PAC card usage, user is not suppose to go edit the memory IP. It's being wrapped up as part for software stack solution. PAC card doesn't expose low level access to the Intel FPGA IP core like DDR4 IP for instance. Thanks. Regards, dlim
  • DNguy4's avatar
    DNguy4
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Dlim,

    That's exactly where i get stuck. I have a design that is working on the A10 evaluation board and it uses memory, 10G MAC/PHyY and PCIe IPs. Now i need to port my design to the PAC card. How do I instantiate those IP? How do i call them and pass data from my logic to them? Is there any instructions or manuals on this?

    Thanks

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    HI, Ok, I get what you are doing now. PAC card design flow is different from traditional Quartus design flow. You can't use Quartus flow to migrate your existing A10 evaluation board design to PAC card. PAC card design flow is developed based on the acceleration stack software where it will instantiate all the periphery IP (like PCIe, Ethernet and DDR4) nicely for user. User is expected to develop FPGA core logic AFU design only to interact with the FPGA periphery IP. You can check out AFU design development guideline in below link. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-afu-dev.pdf You can also find more doc guideline for A10 PAC card in below link https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/acceleration-card-arria-10-gx/documentation.html Thanks. Regards, dlim