Forum Discussion
Occasional ContributorMAXII CPLD ADDRESS GENERATION GLITCHES
Thanks,
I overlooked clk definition in .sdc file which is basically o.k. and should be sufficient to report timing violations in internal logic. Reported Fmax is about 140 MHz, suggesting much of timing margin. I don't see how the glitches can be brought up in address counter and mux logic. I rather guess it's an logic analyzer artifact due to insufficient ground connection or unsuitable level threshold setting. I presume that address lines are not externally driven during glitch period.
Occasional ContributorHi FyM!
Thanks for your comment in advance.
1-sdc file includes just clk and clk_virt ive not included output delays. If u have any concern on this let me know
create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}]
create_clock -name {clk_virt} -period 20.000 -waveform { 0.000 10.000 }
2-Sorry, attached rgb encoder output Attached on .rar
3-Ive tried another project just using IP library lpm_counter for 15 bits, just to count up to 19200 using same clock source of 50MHz/32. Guess what... i still find also what looks as u say, spikes of 50Mhz clock wide (10ns), sometimes other wides..., see below:
As u can see above image, the highest significant bits are also prone to this stuff, and u can notice how the decoded count value is corrupted of course.
on VGA im using just my own sync counter and have simillar issue on real hw as i have with lpm_counter IP library, timing analisys both cases PASS always, as said ive not constraint all paths but clocks.
Let me see your views.
Thanks!!!
BR
Super ContributorThanks,
I overlooked clk definition in .sdc file which is basically o.k. and should be sufficient to report timing violations in internal logic. Reported Fmax is about 140 MHz, suggesting much of timing margin. I don't see how the glitches can be brought up in address counter and mux logic. I rather guess it's an logic analyzer artifact due to insufficient ground connection or unsuitable level threshold setting. I presume that address lines are not externally driven during glitch period.
- Armando1989
Hi FvM, thanks for your answer!
Indeed, it was a darn ground issue... After fiting the shield on lines to GND the artifacts gone... Just cpld aliexpress dev board lacks on sufficient gnd plugs for each channel, which is bad practice but cost and pcb space won the battle..
For vsync and adress buss mux, still experience glitches during vsync bus switchover, as per below image.
Of course, i would need constraint vsync as a clock, since is driving the "swap" signalling
however seems i cannot do generated clock which is that high division ratio, vsync is 60Hz... For those cases, is worth declaring as false path? have u any concern on this?
Thanks!
