MAX V CPLD Development Kit

Sorry for missing to attach the link:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-max-v.html

This is the path where the example located on:

<installation_path>\kits\maxV_5m570z_cpld\examples\golden_top

The schematic is located here:

<installation_path>\kits\maxV_5m570z_cpld\board_design_files\maxv_5m570z_dev\schematic

The userguide in the above link shall explain the connector's connection.

Base on the mapping of the pin name, you can also refer to the requirement of each pin here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-v/pcg-01012.pdf (pin connection guideline)

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html (pinout file)

Thanks.

Eng Wei