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Moe1's avatar
Moe1
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4 years ago

MAX V CPLD Development Kit - Will not work for a simple logic circuit

Intel Community, I recently purchased the Max V Development Kit. I figured out how to use the Quartus Prime Lite and successfully installed the Blaster. Created a simple encoder logic circuit, two in...
  • Moe1's avatar
    Moe1
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hell sstrell,

    You have the right board.

    >> Assuming I have the right board, J6.9 and J6.10 are incorrect for N1 and N2. N1 and N2 are on J6.6 and J6.5 respectively.

    Pins J6.9 and J6.10 are the two AND gate outputs. Also, I accepted the 3.3 LV default. When I test with external switches to the board and outputs to a O-scope, nothing. See attached pictures.

    Am I to have additional pins connected. If I am using 3.3 LV, what must be done with the other power level pins?

    Thank you.

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      4 years ago

      As I stated, N1 and N2 are the MAX V device pin names, but they are actually connected to J6.6 and J6.5, not J6.9 and J6.10. Attach your scope to the correct pins to see the outpu.

      • Moe1's avatar
        Moe1
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        4 years ago

        Hello Sstrell,

        Will check.

        Thank you.