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RLi1's avatar
RLi1
Icon for New Contributor rankNew Contributor
6 years ago

MAX V器件内部振荡器产生的时钟能否作为CPLD逻辑侧的全局时钟使用

MAX V器件内部振荡器产生的时钟能否作为CPLD逻辑侧的全局时钟使用

1 Reply

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    你是说clock共应,可以用在MAX V内部​逻辑侧吗?是可以的

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