Forum Discussion
New ContributorMAX IIZ JTAG Programming
Hi,
1) This version of CPLD my VCCINT is supplied by 1.8V and VCCIO (Bank 1
and 2) with 3.3V. The pin 4 on the JTAG connector, should be attached to
the 1.8V or 3.3V?
The pin 4 should be attach to 3.3V as the input and output buffer is provided by VCCIO pin.
2) Some datasheets say that the TMS should have a 10k pull-up resistor
and TCK should have a pull-down resistor of 10k and some 1k. Which one
is correct for TCK, 10k or 1k?
It should be 10K pull-up on TMS and 1K pull-down for TCK. Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max2/max2_mii51013.pdf - Figure 11–1
Regular ContributorHi,
1) This version of CPLD my VCCINT is supplied by 1.8V and VCCIO (Bank 1
and 2) with 3.3V. The pin 4 on the JTAG connector, should be attached to
the 1.8V or 3.3V?
The pin 4 should be attach to 3.3V as the input and output buffer is provided by VCCIO pin.
2) Some datasheets say that the TMS should have a 10k pull-up resistor
and TCK should have a pull-down resistor of 10k and some 1k. Which one
is correct for TCK, 10k or 1k?
It should be 10K pull-up on TMS and 1K pull-down for TCK. Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max2/max2_mii51013.pdf - Figure 11–1
AzmogodThank you so much for the answers. I am having problems to program my CPLD but i believe it is a bad soldering (uBGA) since when i check the signals on the oscilloscope, my TCK is fine, my TDI is fine but my TDO is always at low. I have only one device on the JTAG Chain, so it could only be this specific device.
