MAX IIZ JTAG Programming
Hello,
I am new to FPGA / CPLD and im having some problems with my project. I am trying to program a CPLD (EPM240ZM68C7) using a USB Blaster and Quartus Prime. Ive been having problems with messages such as "Warning: Uncertain JTAG Chain. Detected 0 devices" and sometime "Error: No device detected". My questions are:
1) This version of CPLD my VCCINT is supplied by 1.8V and VCCIO (Bank 1 and 2) with 3.3V. The pin 4 on the JTAG connector, should be attached to the 1.8V or 3.3V?
2) Some datasheets say that the TMS should have a 10k pull-up resistor and TCK should have a pull-down resistor of 10k and some 1k. Which one is correct for TCK, 10k or 1k?
Thanks
Hi,
1) This version of CPLD my VCCINT is supplied by 1.8V and VCCIO (Bank 1
and 2) with 3.3V. The pin 4 on the JTAG connector, should be attached to
the 1.8V or 3.3V?
The pin 4 should be attach to 3.3V as the input and output buffer is provided by VCCIO pin.
2) Some datasheets say that the TMS should have a 10k pull-up resistor
and TCK should have a pull-down resistor of 10k and some 1k. Which one
is correct for TCK, 10k or 1k?
It should be 10K pull-up on TMS and 1K pull-down for TCK. Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max2/max2_mii51013.pdf - Figure 11–1