Max 10 instability issues, what to check

Missing any other answer, I’ll try to define some points to check, in the hope that could helps any other user with similar issues.

Object: Migrating from old design (Cyclone 1) to new one (MAX10)

Problem: strange behaviours, unstability, FPGA do the same thing but whit random errors and blocking issues.

Solution:

1. Migrate library components, as FIFO
2. Check any new or modified pins and set for most conservative approach (High Z input explicitly set)
3. Check Intel Design Guidelines (Eg: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf ) and apply what is missing:
   1. Clock schemes
   2. Latching of external asynch signals
   3. Reset management
   4. …
4. Optimize for safe state machine, grey coding of states, optimize for stability

Migrating this way, my old design finally passed a quite severe testing procedure, involving also thermal testing at -30 and +64°C

Thank you,

Roberto