Forum Discussion
RobertoP
New Contributor
New ContributorMax 10 instability issues, what to check
Hi.
I have migrated an existing project from a cyclone 1 FPGA to a MAX10 FPGA.
I had no constraints, I have added just master clock that is a 32MHz clock. External signal can be asynchronous (fro...
SyafieqS
Super Contributor
Super ContributorRoberto,
Have you look at the Quartus Design optimization? This could help you to meets the design goals while reducing area, critical path delay, power consumption, and runtime.
RobertoPNew Contributor
New ContributorThank you Syafieq
Already seen.
- Is the reported behaviour a common issue in analogous situation? Never heard before?
- could gray code for machines state improove stability? Or it is just a lucky happening that this work?
- any other Quartus suggested optimization setting to mitigate described behaviour?
- any other VHDL code design aspect to pay attention for?
Thank you a lot,
Roberto
