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RobertoP's avatar
RobertoP
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4 years ago

Max 10 instability issues, what to check

Hi. I have migrated an existing project from a cyclone 1 FPGA to a MAX10 FPGA. I had no constraints, I have added just master clock that is a 32MHz clock. External signal can be asynchronous (fro...
RobertoP's avatar
RobertoP
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4 years ago

Thank you Syafieq

Already seen.

  1. Is the reported behaviour a common issue in analogous situation? Never heard before?
  2. could gray code for machines state improove stability? Or it is just a lucky happening that this work?
  3. any other Quartus suggested optimization setting to mitigate described behaviour?
  4. any other VHDL code design aspect to pay attention for?

Thank you a lot,

Roberto