Honored ContributorHi,
I need to use LVDS on the NE0-Nano development kit, and I have a questions with respect to how to go about it. From what I understand, I have two options:
Honored ContributorJust a short update.
I have managed to get it to work by using differential output buffers. It works fine, but it can only go as fast as the PLL, which for Cyclone IV E speed grade 6 is 472.5MHz. Next step is to get this going with the ALTLVDS megafunction.Honored ContributorCyclone LVDS Megafunctions is just a software SERDES, using DDR registers. You can write equivalent code in your design.
You don't tell the objectives of your project, by the way.Honored ContributorI ma trying to sue FPGA to drive a TFT screen with an FPGA, which results in 7:1 serialisation ratio. My LVDS bit clock is as high as the PLL 472.5MHz, which is not enough for the 60Hz refresh rate.
I was hoping megafunction would allow me to get over that obstacle, but I cannot sense the internal clock that achieves the desired data rate of 583Mbps.Honored ContributorI have managed to write my own SER VHDL code. However, the limiting factor is the PLL frequency. FvM, how can I use the DDR register to doouble the frequency? I tried triggering on either clock edge but Quartus kept complaining and I couldn't compile my design. I would be very grateful if you could point me in the right direction.
Honored ContributorHere's a LVDS receiver example using altddio_in to implement DDR input registers:
chan:
FOR I IN 0 TO N_AD_CHAN - 1 GENERATE
lvds_rcv : altddio_in
GENERIC MAP (
intended_device_family => "Cyclone III",
invert_input_clocks => "ON",
lpm_type => "altddio_in",
power_up_high => "OFF",
width => 1
)
PORT MAP (
datain => AD9222_D(I TO I),
inclock => fastclock,
dataout_h => dataout_h(I DOWNTO I),
dataout_l => dataout_l(I DOWNTO I)
);
PROCESS (fastclock)
BEGIN
IF rising_edge(fastclock) THEN
lvds_sr(I) <= lvds_sr(I)(9 downto 0) & dataout_l(I) & dataout_h(I);
END IF;
END PROCESS;
PROCESS (slowclock)
BEGIN
IF reset = '1' THEN
lvds_rx(I) <= (others => '0');
ELSIF rising_edge(slowclock) THEN
lvds_rx(I) <= lvds_sr(I);
END IF;
END PROCESS;
END GENERATE;many thanks for the example, FvM.
I got it working, however the development kit cannot handle the speed and I get a fair amount of interference, which was expected. Anyway, thanks again.Honored ContributorLVDS is 2.5v but DE0-Nano VCCIO is 3.3v, is fine?
Honored ContributorIn theory it shouldn't work but it worked fine with the TFT panel I was using. I think those input stages on some TFT panels are quite forgiving.
Honored ContributorI think problem is not receiver but output buffer of fpga that can not work safely with 3.3v when configured for 2.5v
Honored ContributorThere are in fact no differential I/O standard supported for 3.3V VCCIO. "can not work safely" is a different thing.
