Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorLooking for high speed benchmark test for the Stratix IV FPGA Dev Kit
I see that the Stratix IV GX development kit with EP4SGX230KF40C2N FPGA is compliant to PCI Express 2.0 x8 (eight lane). Given that each PCIe 2.0 lane can transfer 500 MB/s, eight lanes in aggregate ...
Altera_ForumHonored Contributor
Honored ContributorThe PCI-E resource center on Altera's website:
http://www.altera.com/support/ip/interface-protocols/ips-inp-pcie.html?gsa_pos=2&wt.oss_r=1&wt.oss=pci%20express The achievable bandwidth is highly dependent on your design. This reference design document has some benchmark results with explanations about bandwidth calculations and theoretical limits: http://www.altera.com/literature/an/an456.pdf Jake
