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Its already plugged into my dev board and wont be going anywhere else, so Im not too concerned about the pinout.
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Don't be so sure ...
I had to pull the LCD panel off my Stratix IV GX development kits. The designers forgot to check for voltage compatibility between the LCD and FPGA I/O. The 5V LCDs appear to have pullups on the input data buses, so these signals violate the voltage specification of the FPGA I/O pins when you read from the LCD.
The earlier DE2 boards also have this problem. My solution there was to drive the bus to 3.3V when in idle.
Just be warned :)
Cheers,
Dave
Honored Contributor
