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Altera_Forum's avatar
Altera_Forum
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16 years ago

JTAG and Config, Mutil Voltage, Multi Chip

Hello, I am using an Arria I dev kit to interface to a board that contains 3 FPGAs. The interface (HSMC) provides a JTAG connection plus a number of I/O that I will be using to do PS configura...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Jake, thanks for the answer!

Good point on 3. The termination should be at the source and I am quite far from it (in signal terms.)

The other 3 FGPAs are Arrias (I) also.