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Fourth, I found this out in a hard way, but the 'bts_ddr3' example needs to be restored in the
c:\altera\91\ip\altera\sopc_builder_ip\ to have it compiled correctly. Try to restore it in another path and regenerate its SOPC Builder for NIOS II and recompile in Quartus II, and you will have a few errors reporting some missing Verilog files during Analysis & Synthesis. If you don't regenerate the SOPC Builder, it won't produce any errors, though. My guess is that the DDR3 related file paths are defined as relative paths rather than absolute ones in the design.
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Is the path mentionend above listed in SOPC Builder -> Tools -> Options?
If not, maybe that's the problem...
Honored Contributor
