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Altera_Forum
Honored Contributor
Honored ContributorIssues with Stratix IV E FPGA Dev Kit
We have a Stratix IV E FPGA Development Kit and recently started to use it. But we have several issues on the example designs included in the kit. First, its example designs are segregated i...
Altera_ForumHonored Contributor
Honored ContributorThank you for your reply, jacobjones. I especially appreciate it getting during the weekend.
I would like to answer your question about the timing problems. Since I am more like a software engineer, I had someone look into the TimeQuest report. He said he needs to understand the design to find out if they are critical or can be just ignored. That's a quite a problem because he has never seen the design, and the supplied example projects do not come with Quartus II Block Design Files (.bdf). As far as I know, there is no quick way to convert a VHDL or Verilog file into .bdf.
