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BDura1
New Contributor
7 years agoI forgot to include the program; Apologies!
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
Entity et_ou is PORT(
KEY : IN std_logic_vector(1 downto 0);
LEDR : OUT std_logic_vector(3 downto 0));
End et_ou;
Architecture equations of et_ou is
Begin
LEDR(0) <= KEY(1) and KEY(0);
End equations;