jjang
New Contributor
New ContributorIs There Any Avalon-MM Pipeline slave I/F Example Logic?
i wanna Communicate Logic <-> Nios using Avalon MM Pipeline slave.. is there any Examples? Nios(Qsys, Avalon MM Pipeline Slave) <-> Logic
Forum Discussion
Eliath_G_Intel
Occasional Contributor
Occasional ContributorHi Jongyun,
it is not needed to implement one more clock due to the following:
- New .qsys files include Clock Source component ( clock aggregator)
- When connecting two interfaces:
- Clock input interface fed from the outside system (is exported out of the system, by default)
- Clock Output interface connects to Clock Input Interfaces of other system components.
- Clock column will help to have a quick clock signal connection.
I'd like to share an example design for Avalon Memory-Mapped Slave
in the link, after table one you will find two useful links.
Please let me know how useful the information was to solve the issue.
