Is there a way to include file with macros without having to use `include in every

Question

HiMy  Quartus Prime Pro version is 22.3 During the analysis and sythesis stage, I get compilation issues due to undefined text macros. The text macros are declared in their own file and used in other files of our design. The file is included in the project and looks to be analyzed before the other files which use the macros, yet there are still errors saying undefined text macro.I serach similar cases like :https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Is-there-a-way-to-include-file-with-macros-and-small-modules/td-p/650653But It didnt solve my issue I created a simple project which use only 2 files  :Top file + header fileI'd like to archive and send it ove secure mail , Can you share with me link for it please ?

richardt_altera · Answer

Have you try using the assignment:set_global_assignment -name VERILOG_CU_MODE MFCUhttps://www.intel.com/content/www/us/en/docs/programmable/683463/24-1/verifying-verilog-compilation-unit.htmlYou can find a good explanation here:https://community.intel.com/t5/Intel-Quartus-Prime-Software/SystemVerilog-compile-guards-and-macros/m-p/1293020Regards,Richard Tan

richardt_altera · Answer

Dropping a note to ask if my last reply was helpful to you?Do you need any further assistance from my side?Regards,Richard Tan

ymiler · Answer

Thank youIt fixed my issue

richardt_altera · Answer

I'm pleased to know that your question has been addressed.

Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.

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Is there a way to include file with macros without having to use `include in every

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