Forum Discussion
Luis_R_Intel
New Contributor
New ContributorIs there a way to include file with macros and small modules without having to use `include in every file?
Using the Quartus Prime software during the analysis and sythesis stage, we get compilation issues due to undefined text macros. The text macros are declared in their own file and used in other files...
ak6dn
Regular Contributor
Regular ContributorNo. There is no implicit INCLUDE capability in verilog. You need to use `include <file> in each separately compiled verilog module.
AnandRaj_S_IntelRegular Contributor
Regular ContributorYes, We can use by including the macro files into the file list. If we don't include macro files in file list than we have to `include <file> in each Verilog module.
Please check the attached image.
