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Wow, your system has dual 1GHz? That ADC modules must be expensive though.
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The ADCs are e2v AT84AD001B digitizers. National Semiconductor also has similar devices. The price of the e2v parts is around $250 (on Avnet's web site). The board design is here:
http://www.ovro.caltech.edu/~dwh/carma_board/ (
http://www.ovro.caltech.edu/%7edwh/carma_board/)
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However monitoring for a preset threshold value from ADC must be in realtime anyway, this feature is not going to be a large stream (a sentence or 2) so I hope stratix 3 can handle it.
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Finding a value, or all samples above a value, within a stream from the ADCs would be pretty easy. You'll just have to reproduce the logic for each of the demultiplexed data streams, since the FPGA will have multiple ADC samples per FPGA clock.
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Stratix 3 only support DDR2, isnt it?
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I don't know. My board uses Stratix II LVDS channels to interface to the ADC at either 500Mbps or 1Gbps. There are test results documents at the above link.
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I want to make my system portable, so it wont be in the form of PCI in a PC but through MAC, is this possible? Or can you recommend a more convenient way, as I am new to Altera anyway. :oops:
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You haven't specified whether you want data to be transferred over that link? If you want streaming data off the board, then you might want to use an FPGA with transceivers and use a 10Gb Ethernet link. Alternatively, PCIExpress (PCIe) comes in an external version. ExpressCard's in laptops use PCIe. Perhaps a PCIe link to your box would be cheaper or more useful for streaming data.
Cheers,
Dave
Honored Contributor
