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Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Interfacing Nios II and HMC on Cyclone vGT

Hi everyone, Hope all well and I appreciate if you take a look at this and see if you can help us. We are using Cyclone V GT Dev board to test DDR3 HMC controller. We used 32 bit SGDMA to write int...
Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Kelly,

Thanks for your email. we have always used DDR3A for our application. These are the cases we have tried

1. 40 bit HMC implemented on DDR3A with 32 bit bidi Port and Nios II was unbale to boot up (DDR3A was functional - confirmed by SGDMA data pattern) frequency range from 302 MHZ to 400 MHZ tried

2. 32 bit HMC implemented on DDR3A with 32 bit bidi port and Nios II was unbale to boot up(DDR3A was functional - confirmed by SGDMA data pattern) frequency range from 302 MHZ to 400 MHZ tried

3. Soft memory controller implemented on DDR3A (40 bit) with 302 MHz and Nios II was working fine (256MB DDR3A)

4. Soft memory controller implemented on DDR3A (32 bit) with 302 MHz and Nios II was working fine (256MB DDR3A)

5. Reduced the accisable memory size to 32 MB using HMC and Nios was not working. Soft Controller with same memory size is functional.

During our tests , we have always used DDR3A and never tried DDR3B. I can see regarding instruction master to be 28 bit wide so why it works with soft memory controller but not HMC?

Regards,

Aidin.