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VMR001's avatar
VMR001
Icon for New Contributor rankNew Contributor
6 years ago

Intel FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP not able to write and read from onchip RAM

I have created a design with 3 x 64-bit non-prefetchable BAR, BAR0-1, has 32k RAM (32K space) BAR2-3 has 32K RAM (64K space) BAR 4-5 has 32K RAM (64K space) used Quartus pro 19.4 for implementat...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Could you please use the v19.3 example design instead of v19.4? There is a problem in v19.4, it impact the DMA test, as well as memory read/write test. This problem will be fixed in the next Quartus version release.

Regards -SK