Intel Cyclone V SOC Development Kit

Pin AG2 is connected to HSMA_CLK_IN_P1). Isn't this supposed to be an input pin.

I will need 3 clock outputs (staggered with 33% duty cycle). I'm trying to use an HSMC-SMA adapter board. But based on the schematic of this adapter board, the SMA outputs(J17, J21, J25) are only connected to HSMC pins which are connected to Pin pairs (HSMC_TX_P1/N1, HSMC_TX_P2/N2, HSMC_TX_P3/N3). If these HSMC pin pairs are dedicated to transceivers on the FPGA, is there any other way I can extract the 3 clock signals out of the board(preferably via connectorzied outputs).