Intel cyclone 10GX documentation is conflicting/not clear for unused transceiver pins

Hi

I was using intel cyclone10 GX device in one of our design, I has some doubts in unused transceiver pins.

According to intel documentation on pins guidelines below are recommendations:

1. GXB[L1][C,D]_RX_[0:5]p, GXB[L][1][C,D]_REFCLK_CH[0:5]p - Connect all unused GXB_RXp pins directly to GND, VCCR_GXB, or VCCT_GXB pins."
2. - "GXB[L1][C,D]_RX_[0:5]n, GXB[L][1][C,D]_REFCLK_CH[0:5]n - Connect all unused GXB_RXn pins directly to GND."
3. - "REFCLK_GXB[L1][C,D]_CH[B,T]p - Connect all unused pins either individually to GND or tie all unused pins together through a single 10-kΩ resistor to GND. Ensure that the trace from the pins to the resistor(s) are as short as possible."
4. - "REFCLK_GXB[L1][C,D]_CH[B,T]n - Connect all unused pins either individually to GND or tie all unused pins together through a single 10-kΩ resistor to GND. Ensure that the trace from the pins to the resistor(s) are as short as possible."

But when we ran our design in intel Quartus prime environment we got below:

- The Quartus .pin file says, "-- GXB_GND*: Unused GXB Receiver or dedicated reference clock pin. This pin must be connected to GXB_GND through a 10k Ohm resistor."

we had a confusion here to ground them directly or they need 10k on each pin or one 10k is enough for all the pins then connecting them to GND which one should we follow here. kindly confirm.

Can we use Ceramic caps of value 330uF instead of tantalum caps for 0.9V decoupling ? we took the decoupling reference from cyclone 10GX development kit we have some size constraints.

regards

Sharath M