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New ContributorThe Cyclone V SoC contains several PLLs which can convert the 50MHz clock input into pretty much anything you want. You access a PLL with the altpll IP core in Quartus. The main parameters you will need to set are multiplication factor and the division factor. To get 75MHz from 50MHz you need a multiplication factor of 3 and a division factor of 2. (50MHz X 3) /2 = 75MHz.
You can go much higher frequency than that if you want.
If you have an external clock that is already the frequency you want you can just bring it in to one of the GPIO pins.
In either case you should create design constraints that specify the clock net in your HDL (output of PLL, or GPIO pin) And specify the clock period. The optimizer can use this information to properly build the clock network for you. The software is actually smart enough to figure out what the actual clock pins are, but it can't figure out what frequency they are, so a design constraint is a really good idea. For such a low frequency you can probably get away with a base clock (the 50MHz) and the PLL output.
John S.
