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Altera_Forum
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16 years ago

Inconsistent PCIe reference design BAR mapping in documentation

The PCI Express High Performance Reference Design Application Note (AN 456) documents the following BARs in Table 2 on page 8:

BAR0: 32-bit non prefetchable memory, 256mBytes

BAR1: 32-bit non prefetchable memory, 256kBytes

BAR2: 32-bit non prefetchable memory, 256kBytes

AN 456 does not go into further detail about the reference design hardware that sits behind these BARs. Instead, AN 456 refers the reader back to the PCI Express Compiler User Guide Testbench and Design Example chapter, which describes the reference design hardware. The PCI Express Compiler User Guide documents the following BARs in Table 7-4 on page 7-13:

64-bit BAR 1:0: 32KByte target memory

64-bit BAR 3:2: Read and Write DMA control registers (256 bytes)

64-bit BAR 5:4: 32KByte target memory

To complicate matters, the Stratix IV .sofs delivered with the PCIe High Performance Reference Design match the BARs described in AN 456. I verified this in two different ways:

[1] Used a generic Linux PCIe driver to report the BARs found

[2] Opened each and every Stratix IV Quartus project delivered with the reference design and looked BAR register settings in the PCIe core megawizard

Due to these inconsistencies, I have no way of knowing what hardware sits behind the BARs in my reference design. Has anyone else run into this issue? Have you been able to resolve it?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It turns out that there is no discrepancy between the application note and the compiler user guide. When looking at the mapping alone, it is confusing. However, the following paragraph extracted from page 7-11 of the PCIe Compiler User Guide (version 9.0) clarifies the confusion that I had:

    "altpcierd_rx_tx_downstream_intf—This module processes all downstream read and write requests and handles transmission of completions. Requests addressed to BARs 0, 1, 4, and 5 access the chaining DMA target memory space. Requests addressed to BARs 2 and 3 access the chaining DMA control and status register space using the altpcierd_reg_access module."

    So, the following bars in the documentation map to the same FPGA resources:

    * BAR1:0 (user guide) = BAR5:4 (user guide) = BAR0 (app note) = BAR1 (app note)

    * BAR3:2 (user guide) = BAR2 (app note)