Inconsistent PCIe reference design BAR mapping in documentation

It turns out that there is no discrepancy between the application note and the compiler user guide. When looking at the mapping alone, it is confusing. However, the following paragraph extracted from page 7-11 of the PCIe Compiler User Guide (version 9.0) clarifies the confusion that I had:

"altpcierd_rx_tx_downstream_intf—This module processes all downstream read and write requests and handles transmission of completions. Requests addressed to BARs 0, 1, 4, and 5 access the chaining DMA target memory space. Requests addressed to BARs 2 and 3 access the chaining DMA control and status register space using the altpcierd_reg_access module."

So, the following bars in the documentation map to the same FPGA resources:

* BAR1:0 (user guide) = BAR5:4 (user guide) = BAR0 (app note) = BAR1 (app note)

* BAR3:2 (user guide) = BAR2 (app note)