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Furthermore, You mentioned that I have to implement a controller for the reconfiguration when I unplugged the Quartus and the JTAG. Is the controller in the diagram one in the same?
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What I meant was in your design, you already included the controller to do the bitstream scanning (or let's say it JPEG algorithm reconfiguration). Your whole design (which includes this controller), is loaded once into the FPGA by Quartus, after which you can disconnect Quartus from your board. And your JPEG Algorithm Reconfiguration controller should work (with Quartus disconnected) by scanning in a new algorithm from PC to FPGA via some pre-defined interface. So yes, this controller is already included in your block diagram, named as "Controller (HDL or NIOS)". It has always been the same controller we were talking about. :)
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