Forum Discussion
KennyT_altera
Super Contributor
6 years agoHi,
Did you try the design in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_virtualjtag.pdf page 28? Did your design have a timing closed?
Also, there are example with the terasic on the virtual uart, you can refer to here https://nhiphanlogic.wordpress.com/2014/07/05/virtual-uart-for-the-terasic-de0-nano/
Thanks,
Best regards,
Kenny Tan