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LisaXu's avatar
LisaXu
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Idaville LCC I2C layout trace length

Dear Intel Team: we checked the document <Idaville LCC Platform Design Guide (PDG)>, it shows I2C/SMBUS PCB trace length should be kept in below 30 inch. In my opinion, we ususally use ~3pF/inch f...
Board Debug
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    2 years ago

    Hi Lisa,


    I have got input from the internal team as below:


    All these recommendations in the tables in section 13.1.2 were put together using simulations by our Signal Integrity Team.


    I checked for example the guidelines provided in the Whitley PDG (doc# 574174). Whitley is the platform for ICX-SP, which has a different PCH than ICX-D. Checking table 6-36 in the Whitley PDG I see similar number to the table 13-1 in the Idaville PDG. It seems that even with a different PCH they arrived at similar conclusions.


    You also can run your own simulations and if you think the board is able to handle longer traces, they can do it, but Intel can’t offer support if they deviate from our recommendations.


    Regards,

    Aqid


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I feel like this post is getting "Platform Design" confused with the "Platform Designer" tool found in Quartus since this doesn't sound like it has anything to do with FPGAs.

LisaXu's avatar
LisaXu
Icon for New Contributor rankNew Contributor
2 years ago

Hi Sstrell:

Aqid is helping asking Intel internal team for reply, And I have transferred from other forum,they told me should post in this forum.

Or I donot which forum should I post and It will waste too much time.

Best Regards

Lisa