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wchen50's avatar
wchen50
Icon for New Contributor rankNew Contributor
6 years ago

I used Quartus to generate the soc_system.sopcinfo file, and then use sopc2dts to build the corresponding soc_system.dtb. It seems that everything work fine except that the eth0 is down. Anyone have similar problem or any suggestion?

3 Replies

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hello,

    May I know which FPGA device are you referring to? is it development kit or custom board?

    thank you

    • wchen50's avatar
      wchen50
      Icon for New Contributor rankNew Contributor
      6 years ago

      I am using DE0-Nano-Soc development board, which is using Cyclone V.

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hello.

    Can you share with me the device tree?

    Furthermore, have you tried the default GHRD image came with the board?

    Thank you