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ab4's avatar
ab4
Icon for New Contributor rankNew Contributor
7 years ago

I try to write vhdl program to model an 8bit serial in parallel out shift left register with active high synchronous rest and active low asynchronous set input. am I in the right way?

Library IEEE;

USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_AsyncResetLow is

port(

Q : out std_logic;

Clk :in std_logic;

sync_reset: in std_logic;

D :in std_logic

);

end RisingEdge_DFlipFlop_AsyncResetLow;

architecture Behavioral of RisingEdge_DFlipFlop_AsyncResetLow is

begin

process(Clk,sync_reset)

begin

if(sync_reset='0') then

Q <= '0';

elsif(rising_edge(Clk)) then

Q <= D;

end if;

end process;

end Behavioral;

1 Reply

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    You have to be more clear on your requirements.

    Question and implementation are different, in question you have mentioned "active high synchronous rest" and in code "AsyncResetLow". However your design is correct as per Asynchronous Reset Low.

    For reference go to the template provided in quartus under edit->insert template->VHDL->Full designs->Shift Register.

    Example:

    	process (clk, reset,enable_n )
	begin
		if (reset = '1') then --Active high Asynchronous rest
			
		elsif (rising_edge(clk)) then
 
			if (enable_n = '0') then --Active low synchronous enable
 
			end if;
		end if;
	end process;

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Regards

    Anand