I have cyclone 10 lp FPGA with cypress serial flash as the configuration device. In order to burn my firmware to the flash (using jtag and Active Serial mode) I want to use pof file. Is it a problem?

Hi vicky, I hope you can help me, I have problem to generate the jic file. I generate new NIOS and generate code with eclipse (elf file). From the elf file I generate HEX file for initial the NIOS processor. After synthesis my code I burn the sof file to my board and its work. When I try to generate the jic file I get error the HEX file is not good and that "data in HEX file is overlaps between data blocks at address 8 and address 0" What is problem and how can I fix that? Niv.