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NFerg1's avatar
NFerg1
Icon for New Contributor rankNew Contributor
7 years ago

I designed an FSM, and it's going to states that it shouldn't be able to go to. Please help me understand what my Verilog code is doing.

I am designing a Manchester receiver. The design simulates in modelsim. I synthesized the code and downloaded it to a de10 nano cyclone V fpga to test it, and I used Intel/Altera's signal tap...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

Without seeing your state transition code, it's difficult to figure this out. Decimal 13 is binary 1101, so maybe the most significant bit of your state register is getting set somehow when you want to be going to state 5 (0101).