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ASing173's avatar
ASing173
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5 years ago

I am writting the Verilog code and test bench for 4 bit shync up counter but I am not getting the desired output my code is below I should get cout as increased by 1 but I am not getting it when enable is high.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

You changed your always block so it is no longer clocked. Put it back to always @(posedge clk).

#iwork4intel

  • ASing173's avatar
    ASing173
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    5 years ago

    • ASing173's avatar
      ASing173
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      5 years ago

      still the same