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JGeor12's avatar
JGeor12
Icon for New Contributor rankNew Contributor
6 years ago

I am working with the cyclone V device.Currently i am processing the lvds signals.

The major problem is, i cannot route the input lvds signal between the input to the LVDS_RX IP and input to the lcd externally connected at the same time.Either as input to the lcd or IP is possible....
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Thank you for the qar file ; you are getting this error since you are connecting the reference clk input to the LVDS channel and the fifo.

Quartus wont be able to route the same .

Can you use the other fabric clock in FIFO instead of lvdse_clk ?