New Contributor
Frequent Contributorhey buddy, why not just qar files :)..you have i have to look at your design and instantiated all the IP.
can you please send me the qar files ?
In quartus -> project Arch project -> (Generate .qar )
New ContributorI have attached the QAR file
Frequent ContributorThank you for the qar file ; you are getting this error since you are connecting the reference clk input to the LVDS channel and the fifo.
Quartus wont be able to route the same .
Can you use the other fabric clock in FIFO instead of lvdse_clk ?
New ContributorThank you for the reply.But actually the fifo is not fed by the input lvds clock ,it is fed by the output clock of LVDS_RX ip and it is used for writing .So can you check it and specify on clocks.
