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cyclonevmaster's avatar
cyclonevmaster
Icon for New Contributor rankNew Contributor
2 years ago

how to write data to fpga side sdram on cyclonev

it spends me many days and nights ,any help will be appreciated! i want to write data to fpga side sdram from hps,and my qsys system is do so my code is //gcc 标准头文件 #include <stdio.h> #in...
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Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


I will be working on this case.

Please do allow some time to go through this case. I will reply ASAP.


Regards

Tiwari


  • cyclonevmaster's avatar
    cyclonevmaster
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thanks for your reply!

    I have find out the reason of my “bus error”，it was because that I set the a wrong value of L3 register bit3.it should be 1 to enable the axi master,but i set it to 0 and the master was disabled.

    However,i met another problem when i set correct L3 register.My code like this

    any time i ran the code,it showed "write finished" and then was stuck.

    i am a rookie on cyclonev and i have just learned this forweeks,i am sorry that my description may be unprofessional.if you can present me some easy examples of how to write data from hps to fpga ddr3 on cyclone v, it will help a lot.

    thanks again for your answering my foolish problems