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YigalB's avatar
YigalB
Icon for New Contributor rankNew Contributor
6 years ago

How to use reset input in DE10 lite design?

I assume the DE10 Lite board state can't be assumed after power up and also it should be a better practice to use reset signal - also for the simulator. Can someone provide me a design example with ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Yigal,

You shouldn't need to worry about the default value of register.

Just like what you said, good design practice is to always reset the FPGA design before user start the functional operation. By performing reset operation, then you can force your design to known default state value that you want.

Thanks.

Regards,

dlim

  • YigalB's avatar
    YigalB
    Icon for New Contributor rankNew Contributor
    6 years ago

    Agree to that.

    So how do I perform a reset operation?

    One way is manual: connect a switch and press it.

    Is there an automated way to provide a RESET signal as input to the FPGA?

    So once the image of the design is loaded, I will use it in my logic to bring the FFs to a preset values?

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