How to use reset input in DE10 lite design?

Hi Yigal,

I understand your intention now but sorry, the feature request is not available on DE10 board.

DE10 lite board is just simple demo board meant to showcase FPGA feature and capability. The board is not designed to fit into real system design application.

For your enquiry on FPGA FF,

• If you are designing your own FIFO logic, then you should be able to configure the default state yourself
• Else if you are using Intel FPGA FIFO IP core then it will has its own control mechanism where you can read more about it in below link
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-fifo-15.1.pdf

You can simply google for Intel FPGA IP core user guide to find out more about its usage.

Thanks.

Regards,

dlim