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YigalB's avatar
YigalB
Icon for New Contributor rankNew Contributor
6 years ago

How to use reset input in DE10 lite design?

I assume the DE10 Lite board state can't be assumed after power up and also it should be a better practice to use reset signal - also for the simulator. Can someone provide me a design example with ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Yigal,

You can find all the board component detail of DE10 board in the user manual doc

https://www.intel.com/content/www/us/en/programmable/support/training/university/boards.html

For instance, typically we use on board push button or slide switch to control the reset signal to FPGA design. (refer to user manual chapter 3.3 for the FPGA pin location)

Then for your other questions - FPGA default power on GPIO pin signal stage will be tri-state with weak up. It's not zero.

Thanks.

Regards,

dlim

YigalB's avatar
YigalB
Icon for New Contributor rankNew Contributor
6 years ago

Hi

Yes - i noticed the switches, and I know how to use them to generate input, as they are general purpose.

Yet I wonder: is that a dedicated reset signal on board?

I would like to use this signal as an input to my verilog code, so whenever the board goes through reset, the FPGA content will be reset too. (same way it would have been done if the verilog file would go to chip design - reset is a must).

Using external switch will not be aligned in such case.

I understand that GPIO goes to 3-state. makes sense. However, my question was about the internal FPGA's FF's. I would like them to be set a to certain values when reset occurs.