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Veerappan's avatar
Veerappan
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11 months ago

How to use HPS internal clock in Agilex 7 SOC

Hi,

How to use HPS internal oscillator as a source for both main and peripheral PLL.

I tried by choosing the Internal oscillator in a general configuration in Platform Designer device->device and pin options. But it does not work. How I verified this by reading the main_pllglob register. The address is 0xFFD10048. The VCO source is kept at 0 even though I chose it as an internal oscillator.

Thanks,

Regards,

Veerappan P.

5 Replies

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor

    Hi Veerappan,

    Apologies for the long delay in replying , was on medical leave for 2 weeks and my forum account access got revoked, just manage to regain access this week.

    I will look into this case and feedback to you later, once again I'm sorry for the long response delay.

    Thanks

    Regards

    Kian

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor

    Hi Veerappan,

    Sorry for the delay, was discussing your 3 forum issues with our team. Could you give more details like what other changes in your configuration and the steps you use to build, program and read back the register, additional logs /design files would be helpful?

    I will try to see whether I could source an Agilex 7 SOC on my side to replicate based on your configuration.

    Thanks

    Regards

    Kian

    • Veerappan's avatar
      Veerappan
      Icon for New Contributor rankNew Contributor

      Hi khtan,

      I am using ARMDS to program, debug the uboot and read register value. Actually My question is how to configure HPS internal oscillator as source for both main and peripheral PLL.

      Thanks,

      Regards,

      Veerappan P.

      • KianHinT_altera's avatar
        KianHinT_altera
        Icon for Frequent Contributor rankFrequent Contributor

        Hi Veerappan,

        Sorry for the hold up, I've checked with our embedded team and also factory guy on this regarding the documentation mentioning about internal OSC usage and also testing out the Quartus

        Internal OSC is not available as source for both main and peripheral PLL.

        The confusion is actually because of the documentation statement that mentioned about the inputs to PLL but on the note below, it does mentioned that Internal OSC cannot be used under normal circumstances. Internal OSC is meant for bring up HPS, after bring up HPS will switch to HPS_OSC_CLK

        even though you configured at Device and pin options to use internal OSC

        but in HPS QSYS, main PLL and peripheral PLL input clocks (under internal clocks and output clocks tab) are limited to external OSC or FPGA to HPS free clock(if enabled) only

        enable FPGA-to-HPS free clock (input clocks tab)

        Hope that clears up the OSC issue not locking and still remaining default to External OSC when reading the register back.

        Thanks and sorry for the delay in getting back on this.

        Regards

        Kian